When products are sold to original equipment manufacturers (OEMs), the products are usually accompanied by device specifications. The specifications typically include acceptable operating conditions, connection recommendations, direct current (DC) specifications, and alternating current (AC) specifications. The device is commonly expected to perform according to the specifications.
Product manufacturers perform certain tests on the devices in order to guarantee the product complies with the specifications. A group of key electronic companies proposed a technique whereby integrated circuits (i.e., chips) on a printed circuit board could be tested easily by incorporating software-controlled hardware into the integrated circuit during manufacturing. This technique was approved by the well known Institute of Electrical and Electronics Engineers (IEEE) as IEEE Standard 1149.1-1990. Because the group of key electronic companies was known as the Joint Test Action Group, the terms “IEEE Standard 1149.1” and “JTAG Standard” often are used interchangeably.
The IEEE 1149.1 or JTAG Standard specifies the hardware and software needed to enable testing of chips. The JTAG Standard provides for a test access port architecture for testing chips.
Typically, integrated circuits are manufactured and tested in large volumes via a test access port (TAP) or multiple TAPs. Prior to performing certain tests, several integrated circuits may be chained together via the interfaces of their respective TAPs). Alternatively, multiple input pins on a single integrated circuit may be tested through the TAP interface of the integrated circuit under test. As is well known, each TAP interface has four (or optionally five) pins, any one of which may be referred to as a “boundary pin” or a “test access pin.” A test clock (TCK) pin receives a test clock signal for the device under test. A test mode select (TMS) pin accepts commands to select particular test modes. A test data in (TDI) pin accepts data into the device under test. A test data output (TDO) pin sends data out from the device under test.
In many integrated circuits, fuses or other non-volatile memory are used to store information or identification, form connections for redundancy, configuration, etc. For example, fuses can be “blown” or “programmed” in a pattern to indicate the state of the integrated circuit (e.g., operating frequency, bus ratio, cache repair status, etc.).
Sometimes testing several integrated circuits in parallel can be problematic. For example, it can be difficult to independently read and control individual devices connected in parallel. One solution is to connect the devices in parallel except that each device has its own TDO and TDI that are read out individually. This method requires separate control interfaces and connections to and from each device, however, and therefore is cumbersome and inefficient.